Semiconductor memory device and method of forming the same

ABSTRACT

A semiconductor device includes a substrate with a metal line embedded in the substrate, a dielectric layer disposed on the substrate, a bottom electrode via extending through the dielectric layer and landing on a top surface of the metal line, a bottom electrode disposed on a top surface of the bottom electrode via, a magnetic tunneling junction stack disposed on a top surface of the bottom electrode, and a top electrode disposed on the magnetic tunneling junction stack. A lower portion of the bottom electrode via includes a first metal, and an upper portion of the bottom electrode via includes a second metal that is different from the first metal.

PRIORITY DATA

This is a divisional application of U.S. application Ser. No.16/998,911, filed Aug. 20, 2020, which is herein incorporated byreference in its entirety.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experiencedexponential growth. Technological advances in IC materials and designhave produced generations of ICs where each generation has smaller andmore complex circuits than the previous generation. In the course of ICevolution, functional density (i.e., the number of interconnecteddevices per chip area) has generally increased while geometry size(i.e., the smallest component (or line) that can be created using afabrication process) has decreased. This scaling down process generallyprovides benefits by increasing production efficiency and loweringassociated costs. Such scaling down has also increased the complexity ofprocessing and manufacturing ICs.

One advancement in some IC design and fabrication has been thedeveloping of non-volatile memory (NVM), and in particular to magneticrandom-access memory (MRAM). MRAM offers comparable performance tovolatile static random-access memory (SRAM) and comparable density withlower power consumption to volatile dynamic random access memory (DRAM).Compared to NVM Flash memory, MRAM may offer faster access times andsuffer less degradation over time. An MRAM cell is formed by a magnetictunneling junction (MTJ) comprising two ferromagnetic layers which areseparated by a thin insulating barrier, and operates by tunneling ofelectrons between the two ferromagnetic layers through the insulatingbarrier. In operation, the variable states (e.g., logical “0” or “1”state) of an MRAM cell is typically read by measuring the resistance ofthe MTJ. Due to magnetic tunnel effect, the resistance of the MTJchanges with the variable magnetic polarity. When a voltage bias isapplied across a combined structure of a top metal line (e.g., a bitline), a top electrode via, a top electrode, a MTJ, a bottom electrode,a bottom electrode via, and a bottom metal line (e.g., a word line), onecan obtain a series resistance of the combined structure when a currentflowing therethrough is measured. The series resistance includes theresistance of the MTJ and additional resistance. The additionalresistance shall be reduced to or kept at a desirable value as low aspossible in order to improve sensitivity and speed of the MRAM cell.Although existing approaches in MRAM device formation have generallybeen adequate for their intended purposes, they have not been entirelysatisfactory in all respects. For example, a high-resistive bottomelectrode via (BEVA) is often a major contributor to the additionalresistance in an MRAM cell and thus degrades memory circuit performance.Accordingly, there exists a need for improvements in this area.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is best understood from the following detaileddescription when read with the accompanying figures. It is emphasizedthat, in accordance with the standard practice in the industry, variousfeatures are not drawn to scale and are used for illustration purposesonly. In fact, the dimensions of the various features may be arbitrarilyincreased or reduced for clarity of discussion.

FIGS. 1A and 1B illustrate perspective views of a magnetic tunnelingjunction (MTJ) within a magnetic random-access memory (MRAM) cell.

FIG. 1C illustrates an MRAM cell array, in accordance with anembodiment.

FIGS. 2A and 2B show a flow chart of a method for forming an MRAM cellarray, according to aspects of the present disclosure.

FIGS. 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, and 18illustrate cross-sectional views of a semiconductor structure during afabrication process according to the method of FIGS. 2A-2B, inaccordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly. Still further, when anumber or a range of numbers is described with “about,” “approximate,”and the like, the term is intended to encompass numbers that are within+/−10% of the number described, unless otherwise specified. For example,the term “about 5 nm” encompasses the dimension range from 4.5 nm to 5.5nm.

The present disclosure is generally related to semiconductor devices andfabrication methods. Some aspects of the present disclosure relate tomagnetic random-access memory (MRAM) cells. More particularly, thepresent disclosure is related to providing an MRAM cell with a bottomelectrode via (BEVA) comprising at least two different metals (e.g.,copper and tungsten), which reduces additional resistance in a currentpath through the MRAM cell. By having a low-resistive current path,sensitivity and speed of the MRAM cell are improved.

FIGS. 1A and 1B illustrate perspective views of a magnetic tunnelingjunction (MTJ) 100 within an MRAM cell. The MTJ 100 includes an upperferromagnetic plate 102 and a lower ferromagnetic plate 104, which areseparated by a thin insulating layer 106, also referred to as a tunnelbarrier layer. One of the two ferromagnetic plates (e.g., the lowerferromagnetic plate 104) is a magnetic layer that is pinned to anantiferromagnetic layer, while the other ferromagnetic plate (e.g., theupper ferromagnetic plate 102) is a “free” magnetic layer that can haveits magnetic field changed to one of two or more values to store one oftwo or more corresponding data states.

The MTJ 100 uses tunnel magnetoresistance (TMR) to store magnetic fieldson the upper and lower ferromagnetic plates 102 and 104. Forsufficiently thin insulating layer 106 thicknesses (e.g., about 100angstrom (A) or less), electrons can tunnel from the upper ferromagneticplate 102 to the lower ferromagnetic plate 104. Data may be written tothe cell in a variety of ways. In one method, current is passed betweenthe upper and lower ferromagnetic plates 102 and 104, which induces amagnetic field stored in the free magnetic layer (e.g., the upperferromagnetic plate 102). In another method, spin-transfer-torque (STT)is utilized, wherein a spin-aligned or polarized electron flow is usedto change the magnetic field within the free magnetic layer with respectto the pinned magnetic layer. Other methods to write data may be used.Nonetheless, various data writing methods include changing the magneticfield within a free magnetic layer with respect to a pinned magneticlayer.

The resistance of the MTJ 100 changes in accordance with the magneticfields stored in the upper and lower ferromagnetic plates 102 and 104,due to the magnetic tunnel effect. For example, in FIG. 1A, the magneticfields of the upper and lower ferromagnetic plates 102 and 104 arealigned (e.g., arrows 112A and 114A), resulting in a low-resistancestate (i.e., a logical “0” state). In FIG. 1B, a current has been passedthrough the MTJ 100 to induce a change in the magnetic field of themagnetic free layer (e.g., upper ferromagnetic plate 102). Therefore,after this data write operation, the magnetic fields in the upper andlower ferromagnetic plates 102 and 104 oppose one another (e.g., arrows112B and 114B), which gives rise to a high resistance state (i.e., alogical “1” state). Hence, by measuring the resistance between the upperand lower ferromagnetic plates 102 and 104, read circuitry coupled tothe MTJ 100 can discern between “0” and “1” data states.

FIG. 1C illustrates an MRAM cell array 120, which includes M rows(words) and N columns (bits) of MRAM cells. Each MRAM cell comprises anMTJ 100. Word lines WL₁, WL₂, . . . WL_(M) extend across respective rowsof memory cells and bit lines BL₁, BL₂, . . . BL_(N) extend alongcolumns. The MRAM cells are sandwiched between the metal grids of wordlines and bit lines. Each MRAM cell further includes a top electrodeconnected to a metal line above (e.g., a bit line) through a topelectrode via and a bottom electrode connected to a metal line under(e.g., a word line) through a bottom electrode via. When data is writtento or read from a MRAM cell, a word line (WL) is asserted to select arow and an appropriate bias is applied to an individual bit line (BL) towrite or read respective value to or from the respective MRAM cell ofthe selected row. Driven by the appropriate bias, a current flowingthrough a combined structure of the bit line, the top electrode via, thetop electrode, the MTJ, the bottom electrode, the bottom electrode via,and the word line is measured. One can thus obtain a series resistanceof the combined structure from values of the bias and current and derivethe resistance of the MTJ. Accordingly, additional resistance other thanthe resistance of the MTJ itself shall be reduced to or kept at adesirable value as low as possible to safeguard sensitivity and speed ofthe MRAM cell. There is, however, a large portion of additionalresistance to be expected due to the bottom electrode via. In someembodiments, titanium nitride (TiN) and tungsten (W) are widely used forforming the bottom electrode via. Although copper (Cu) has a much lowerresistivity than TiN and W, process flows in the art avoid using Cu forthe bottom electrode via, due to its high diffusion capability, whichcan be detrimental to the MTJ disposed above the bottom electrode via ifdiffusion occurs. The present disclosure provides a method forfabricating MRAM cells with low-resistive copper-containing bottomelectrode vias. As a result, sensitivity and speed of the MRAM cells areimproved.

FIGS. 2A and 2B illustrate a flow chart of a method 200 for forming anMRAM cell array in accordance with an embodiment. The method 200 ismerely an example, not intended to limit the present disclosure beyondwhat is explicitly recited in the claims. Additional operations can beprovided before, during, and after the method 200, and some operationsdescribed can be replaced, eliminated, or moved around for additionalembodiments of the method. The method 200 is described below inconjunction with FIGS. 3-18 , which illustrate various cross-sectionalviews of a portion of an MRAM cell array during fabrication stepsaccording to the method 200.

At operation 202, the method 200 (FIG. 2A) provides, or is providedwith, a device structure 300 having a substrate 302, such as shown inFIG. 3 . The substrate 302 is a silicon substrate in the illustratedembodiment. Alternatively, the substrate 302 may comprise anotherelementary semiconductor, such as germanium; a compound semiconductorincluding silicon carbide, gallium nitride, gallium arsenide, galliumphosphide, indium phosphide, indium arsenide, and indium antimonide; analloy semiconductor including silicon germanium, gallium arsenidephosphide, aluminum indium phosphide, aluminum gallium arsenide, galliumindium arsenide, gallium indium phosphide, and gallium indium arsenidephosphide; or combinations thereof. In another embodiment, the substrate302 includes indium tin oxide (ITO) glass. In various embodiments, thesubstrate 302 is a wafer, such as a silicon wafer, and may include oneor more epitaxially grown semiconductor layers in its upper portion.

The substrate 302 is disposed with an interconnect structure 304 on itsupper surface. The interconnect structure 304 includes an inter-metaldielectric (IMD) layer 306 and a metal line 308 which extendshorizontally in the IMD layer 306. The IMD layer 306 can be an oxide,such as silicon dioxide, a low-k dielectric material such as carbondoped oxides, or an extreme low-k dielectric material such as porouscarbon doped silicon dioxide. The metal line 308 can be made of a metal,such as aluminum (Al), Cu, or combinations thereof.

At operation 204, the method 200 (FIG. 2A) deposits a dielectric layer310 over the interconnect structure 304, such as shown in FIG. 4 . Inthe illustrated embodiment, the dielectric layer 310 is in a form ofstacking sublayers, for example, a silicon carbonitride (SiCN) layer 310a, an aluminum oxide (AlO_(x)) layer 310 b, an undoped silicon oxideglass (USG) layer 310 c, and a capping layer 310 d, which are blanketdeposited over a top surface of the interconnect structure 304. Thecapping layer 310 d is nitrogen free and comprises materials such assilicon-rich oxide (SRO), silicon oxycarbide, the like, or a combinationthereof. The capping layer 310 d is also used as a bottomanti-reflective coating (BARC) in some embodiments. Therefore, thecapping layer 310 d is also referred to as nitrogen-free anti-reflectioncoating (NFARC) layer. The dielectric layer 310 can be formed by avariety of techniques, including chemical vapor deposition (CVD),low-pressure CVD (LP-CVD), plasma-enhanced CVD (PE-CVD), sputtering, andphysical vapor deposition (PVD), and the like. In some embodiments, theSiCN layer 310 a has a thickness about 150-200 Å, the AlO_(x) layer 310b has a thickness about 40-60 Å, the USG layer 310 c has a thicknessabout 500-650 Å, and the NFARC layer 310 d has a thickness about200-1500 Å.

After the dielectric layer 310 is formed, a mask 312, such as aphotoresist mask, is then formed over the dielectric layer 310. Anetching process 314 is then carried out with the mask 312 in place topattern the dielectric layer 310. The etching process 314 can beperformed by a suitable dry etch operation. In some embodiments, the dryetch includes reactive ion etch (RIE) adopting fluorine-containinggases. In some embodiments, the dry etch operation can be any suitabledielectric etch to form a via trench 316 in a metallization structure ofconventional CMOS technology. The via trench 316 exposes a portion ofthe metal line 308. The mask 312 can be removed after the etching.

At operation 206, the method 200 (FIG. 2A) forms a diffusion barrierlayer 318 that is blanket lined over sidewalls and bottom of the viatrench 316 and over the dielectric layer 310. The diffusion barrierlayer 318 may comprise a conductive material, such as, for example,titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride(TaN), cobalt (Co), or a combination of one or more of the foregoing.The diffusion barrier layer 318 may be deposited through a process suchas atomic layer deposition (ALD), CVD, PVD or other suitable methods.For example, the diffusion barrier layer 318 may include three sublayersand be formed by sequentially depositing a tantalum layer (e.g., about10 Å), a tantalum nitride layer (e.g., about 20 Å), and a cobalt layer(e.g., about 20 Å) in PVD processes at a temperature above 300 degreesin Celsius. Subsequently, a first deposition of bottom electrode viamaterial 320 a is performed. The bottom electrode via material 320 a bedeposited over the diffusion barrier layer 318 in the via trench 316.The resultant structure is illustrated in FIG. 5 . The first depositedbottom electrode via material 320 a may be formed by a variety oftechniques, such as high-density ionized metal plasma (IMP) deposition,high-density inductively coupled plasma (ICP) deposition, sputtering,CVD, PVD, LP-CVD, PE-CVD, and the like. In the illustrated embodiment,the first deposited bottom electrode via material 320 a is Cu and isformed of an electroplating operation with a Cu seed layer depositedover the diffusion barrier layer 318 in the via trench 316. Theelectroplating operation stops when Cu reaches a predetermined heightH1. In some embodiments, the height H1 ranges from about 400 Å to about1000 Å, such as 620 Å in a specific example. Compared with TiN and Wthat have been widely used for forming bottom electrode via, Cu has amuch smaller resistivity that is only about one tenth ( 1/10) of TiN andabout one third (⅓) of W. By using Cu as a bottom portion of the bottomelectrode via, the overall resistance of the bottom electrode via can beeffectively reduced.

At operation 208, the method 200 (FIG. 2A) performs a second depositionof bottom electrode via material 320 b in the via trench 316 and overthe diffusion barrier layer 318, such as shown in FIG. 6 . The bottomelectrode via material 320 b comprises a metal different from the bottomelectrode material 320 a. The second deposited bottom electrode viamaterial 320 b may be formed by a variety of techniques, such ashigh-density IMP deposition, high-density ICP deposition, sputtering,CVD, PVD, LP-CVD, PE-CVD, and the like. In the illustrated embodiment,the bottom electrode via material 320 b is W and is formed in aDamascene operation followed by a planarization process, such as achemical mechanical polishing (CMP), an etch operation, or combinationsthereof, to remove excessive conductive material. The planarizationprocess also removes the diffusion barrier layer 318 from locationsoutside the via trench 316 and thus exposes the top surface of thedielectric layer 310. The capping layer 310 d in the top portion of thedielectric layer 310 may also be removed in the planarization process.The resultant structure after the planarization process is illustratedin FIG. 7 . If the opening of the via trench 316 is wider than apredetermined value, a dishing effect may occur in the second depositedbottom electrode via material 320 b as a result of planarizationprocess. The dotted line 321 in FIG. 7 represents an alternative topsurface of the second deposited bottom electrode via material 320 b if adishing effect occurs. The thickness H2 of the second deposited bottomelectrode via material 320 b is measured at its thinnest position, suchas the bottommost point of the dotted line 321.

The first deposited bottom electrode via material 320 a and the seconddeposited bottom electrode via material 320 b collectively define abottom electrode via 320. In other words, the bottom electrode via 320includes a lower portion filled with a first conductive material 320 aand an upper portion filled with a second conductive material 320 b thatis different from the first conductive material 320 a. As discussedabove, in the illustrated embodiment, the first conductive material 320a is Cu and the second conductive material 320 b is W. Notably, thesecond conductive material 320 b functions as a capping layer to blockthe diffusion of Cu into upper layers where a magnetic tunnelingjunction (MTJ) stack will subsequently be formed. Diffusion of Cu intothe MTJ stack is detrimental to operations of MRAM cells. Therefore, invarious embodiments, the thickness H2 of the conductive material 320 bhas a minimum thickness of about 120 Å. If the thickness H2 is smallerthan 120 Å, the capping layer would not effectively block Cu diffusion.In some embodiments, the thickness H2 ranges from about 120 Å to about300 Å, such as about 155 Å in a specific example. In some embodiments, aratio between the thicknesses of Cu and W (H1/H2) ranges from about 2:1to about 5:1, such as about 4:1 in a specific example. If H1/H2 is lessthan 2:1, the upper portion comprising W may be too thick and theresistance of the bottom electrode via may become too large andnegatively impact MRAM cell performance. If H1/H2 is larger than 5:1,the W layer may be too thin to effectively block the diffusion of Cu andyet negatively impact MRAM cell performance. By having Cu as a majorportion of the bottom electrode via without causing Cu diffusion intoMTJ stacks, the resistance of the bottom electrode via can be reduced byabout 60% to about 90% in some embodiments. Accordingly, the overallseries resistance in the current path through the MRAM cell is alsoreduced. Further, the series resistance reduction method is easilycompatible with back-end-of-line (BEOL) process flows, providing betterMRAM operations with controlled manufacturing cost.

At operation 210, the method 200 (FIG. 2A) forms a bottom electrodelayer 322 over the dielectric layer 310 and in contact with the bottomelectrode via 320, such as shown in FIG. 8 . The bottom electrode layer322 may be a conductive material, such as, for example, TiN, TaN, Ti,Ta, or a combination of one or more of the foregoing. The bottomelectrode layer 320 may be deposited through a process such as ALD, CVD,PVD or other suitable methods. For example, the bottom electrode layer322 may be formed by depositing TiN in a PVD process at a temperatureabove 300 degrees in Celsius. The top surface of the bottom electrodelayer 322 may have a non-planar top surface after deposition and may beplanarized in one or more CMP processes thereafter. In some embodiments,the bottom electrode layer 322 has a thickness about 140-160 Å.

At operation 212, the method 200 (FIG. 2A) forms a magnetic tunnelingjunction (MTJ) stack 330 over an upper surface of the bottom electrodelayer 322, such as shown in FIG. 9 . In the illustrated embodiment, theMTJ stack 330 includes a lower ferromagnetic electrode layer 332 (whichcan have a pinned magnetic orientation) and an upper ferromagneticelectrode layer 342 (which can have a free magnetic orientation). Atunneling barrier layer 340 is disposed between the lower and upperferromagnetic electrodes layers 332 and 342. The lower ferromagneticelectrode layer 332 can be a synthetic anti-ferromagnetic (SAF)structure that includes a bottom pinned ferromagnetic layer 334, a toppinned ferromagnetic layer 338, and a metal layer 336 sandwiched betweenthe bottom and top pinned ferromagnetic layers 334 and 338. Each layerof the MTJ stack 330 is disposed through appropriate layer growthtechniques. Some layer growth techniques comprise sputter deposition,molecular beam epitaxy (MBE), pulsed laser deposition (PLD), ALD,electron beam (e-beam) epitaxy, chemical CVD, or derivative CVDprocesses further comprising LP-CVD, atomic layer CVD (AL-CVD),ultrahigh vacuum CVD (UHV-CVD), reduced pressure CVD (RP-CVD), or anycombinations thereof.

In some embodiments, the upper ferromagnetic electrode layer 342comprises Fe, Co, Ni, FeCo, CoNi, CoFeB, FeB, FePt, FePd, or the like,and has a thickness ranging between approximately 8 Å and approximately13 Å. In some embodiments, the tunneling barrier layer 340 provideselectrical isolation between the upper ferromagnetic electrode layer 342and the lower ferromagnetic electrode layer 332, while still allowingelectrons to tunnel through the tunneling barrier layer 340 under properconditions. The tunneling barrier layer 340 may comprise, for example,magnesium oxide (MgO), aluminum oxide (e.g., Al₂O₃), NiO, GdO, Ta₂O₅,MoO₂, TiO₂, WO₂, or the like. Further, the tunneling barrier layer 340may be, for example, about 100-200 Å thick. In an embodiment, the bottompinned ferromagnetic layer 334 includes a CoFeB film. Alternatively, thebottom pinned ferromagnetic layer 334 may comprise other materials, suchas CoFeTa, NiFe, Co, CoFe, CoPt, CoPd, FePt, or an alloy of Ni, Co, andFe. In an embodiment, the metal layer 336 includes ruthenium (Ru).Alternatively, the metal layer 336 may include other suitable material,such as Ti, Ta, Cu, or Ag. In some embodiments, the top pinnedferromagnetic layer 338 includes a ferromagnetic material substantiallysimilar to that of the bottom pinned ferromagnetic layer 334. Forexample, the top pinned ferromagnetic layer 338 includes a CoFeB film.In various embodiments, the MTJ stack 330 has a total height in a rangefrom about 200 Å to about 400 Å.

At operation 214, the method 200 (FIG. 2B) forms a top electrode layer350 over an upper surface of the MTJ stack 330, such as shown in FIG. 10. The top electrode layer 350 may be a conductive material, such as, forexample, TiN, TaN, Ti, Ta, or a combination of one or more of theforegoing. The top electrode layer 350 may be deposited through aprocess such as ALD, CVD, PVD or other suitable methods. For example,the top electrode layer 350 may be formed by depositing TiN in a PVDprocess at a temperature above 300 degrees in Celsius. The top surfaceof the top electrode layer 350 may have a non-planar top surface afterdeposition and may be planarized in one or more CMP processesthereafter. In some embodiments, the bottom electrode layer 322 and thetop electrode layer 350 include different conductive material, such asTa, TaN, or a combination of Ta and TaN in the bottom electrode layer322, whereas TiN in the top electrode layer 350. In some embodiments,the top electrode layer 350 has a thickness about 250-300 Å. In theillustrated embodiment, the top electrode layer 350 has a largerthickness than the bottom electrode layer 322.

At operation 216, the method 200 (FIG. 2B) forms a hard mask layer 360over the top electrode layer 350, such as shown in FIG. 11 . The hardmask layer 360 may include one or more patterning layers. In someembodiments, the hard mask layer 360 comprises dielectric material suchas silicon oxide, silicon nitride, silicon oxynitride, amorphous carbon(APF), or suitable combination thereof. The hard mask layer 360 may bedeposited through a process such as CVD or other suitable methods.Operation 216 further includes patterning the hard mask layer 360 byphotolithography and etching processes, such as shown in FIGS. 12 and 13. The photolithography and etching processes may first form and patterna resist layer 370 over the hard mask layer 360, then pattern the hardmask layer 360 using the patterned resist layer 370 as an etching mask.The resist layer 370 may include two or more layers, such as a bottomanti-reflective coating (BARC) layer 372 and a photosensitive layer 374in the illustrated embodiment. An exemplary photolithography process mayinclude a lithographic exposure to perform on the photosensitive layer374 that exposes selected regions to radiation. The exposure causes achemical reaction to occur in the exposed regions of the photoresist.After exposure, a developer is applied to the photoresist. The developerdissolves or otherwise removes either the exposed regions in the case ofa positive resist development process or the unexposed regions in thecase of a negative resist development process. Suitable positivedevelopers include TMAH (tetramethyl ammonium hydroxide), KOH, and NaOH,and suitable negative developers include solvents such as n-butylacetate, ethanol, hexane, benzene, and toluene. After the photoresist isdeveloped, a pattern formed in the photosensitive layer 374 istransferred to the BARC layer 372 by selectively etching throughopenings in the developed photosensitive layer 374, resulting in apatterned resist layer 370. Subsequently, such as shown in FIG. 13 , theexposed portions of the hard mask layer 360 may be removed by an etchingprocess 376, such as wet etching, dry etching, Reactive Ion Etching(RIE), ashing, and/or other etching methods, resulting in a patternedhard mask layer 360. The patterned hard mask layer 360 may be in a formof a pillar with a circular shape from a top view. The shape of thepatterned hard mask layer 360 will be transferred to the top electrodelayer 350 and the underlying MTJ stack 330 by patterning methodsdisclosed in subsequent embodiments herein. After patterning the hardmask layer 360, the resist layer 370 may be removed.

At operation 218, the method 200 (FIG. 2B) etches the top electrodelayer 350 using the patterned hard mask layer 360 as an etching mask,such as shown in FIG. 13 . Operation 218 may use a dry etching, a wetetching, or other suitable etching processes. For example, a dry etchingprocess may implement an oxygen-containing gas, a fluorine-containinggas (e.g., CF₄, SF₆, CH₂F₂, CHF₃, and/or C₂F₆), a chlorine-containinggas (e.g., Cl₂, CHCl₃, CCl₄, and/or BCl₃), a bromine-containing gas(e.g., HBr and/or CHBR₃), an iodine-containing gas, other suitable gasesand/or plasmas, and/or combinations thereof. For example, a wet etchingprocess may comprise etching in diluted hydrofluoric acid (DHF);potassium hydroxide (KOH) solution; ammonia; a solution containinghydrofluoric acid (HF), nitric acid (HNO₃), and/or acetic acid(CH₃COOH); or other suitable wet etchant. In some embodiments, theetching process is an RIE process under process parameters such as asource power ranging from about 900 W to about 1200 W, a bias voltageranging from about 0 V to about 500 V, a gas flow ranging from about 10sccm to about 200 sccm, and a temperature ranging from about 15 degreesin Celsius to about 55 degrees in Celsius. The etchant gas may includeCl₂, SiCl₄, BCl₃, NF₃, N₂, H₂, CH₄, HBr, He, Ar, or a combinationthereof. After etching the top electrode layer 350, the patterned hardmask layer 360 may be removed.

At operation 220, the method 200 (FIG. 2B) etches the MTJ stack 330 andthe bottom electrode layer 322 using the patterned top electrode layer350 as an etching mask, such as shown in FIG. 14 . Operation 220includes an etching process to etch through the MTJ stack 330 and thebottom electrode layer 322. In an embodiment, the etching process is anisotropic dry etching process. In some embodiments, the etching processtransfers a pattern defined in the top electrode layer 350 such as apillar array (e.g., cylindrical pattern) into the MTJ stack 330 first,followed by the removal of portions of the bottom electrode layer 322using the patterned top electrode layers 350 and the patterned MTJ stack330 together as an etching mask. In some embodiments, the etchingprocess etches the MTJ stack 330 and the lower electrode layer 322together with no intermediate etching step. In some embodiments, theetching process in operation 218 and the etching process in operation220 are one etching step, which etches the top electrode layer 350, theMTJ stack 330, and the bottom electrode layer 322 together with nointermediate etching step. After patterning the top electrode layer 350,the MTJ stack 330, and the bottom electrode layer 320, for the sake ofsimplicity of description, the patterned top electrode layer 350 isdenoted as the top electrode 350, the patterned MTJ stack 330 is denotedas the MTJ 330, and the patterned bottom electrode layer 322 is denotedas the bottom electrode 322.

In some embodiments, the etching process comprises applying a wetetchant or a plasma etchant for a predetermined period of time. In someembodiments, operation 220 uses an end-point control method to preciselycontrol the etching time. An end-point control analyzes emittedresiduals in real time during an etching process, such as by inspectinglight spectra emitted by a plasma during a plasma etching with anoptical emission spectroscopy (OES). When material compositions from thebottom electrode 322 diminish, the etching process slightly over etchesinto a top portion of the dielectric layer 310, such that the topsurface 354 of the USG layer 310 c is below the bottom surface of thebottom electrode 322 for a distance H3. In one example, the distance H3is about 100 Å. In some embodiment, In the illustrated embodiment, thebottom electrode 322 is wider than a top surface of the bottom electrodevia 320, and a portion of the USG layer 310 c remains directly under thebottom electrode 322, as highlighted in the dotted circle 356 in FIG. 14. Notably, the over etch keeps the top surface 354 above an interfacebetween W/Cu of the bottom electrode via 320 for a distance H4. Invarious embodiments, the distance H4 is at least 30 Å. If the distanceH4 is less than 30 Å, it runs the risk of Cu diffusing into thefabrication apparatus and causing Cu contamination. In some embodiments,a ratio of the H3/H4 is about 0.5:1 to about 4:1. If H3/H4 is less than0.5:1, the over etch may not be sufficient to ensure the completepatterning of the bottom electrode layer 322 under various processvariations. If H3/H4 is larger than 4:1, there is high risk of Culeaking and contamination.

At operation 222, the method 200 (FIG. 2B) forms a sidewall spacer layer362 covering sidewalls of the top electrode 350, the MTJ 330, and thebottom electrode 320, as well as the top surface of the top electrode350 and the dielectric layer 310, such as shown in FIG. 15 . Thesidewall spacer layer 362 may comprise a dielectric material, such assilicon oxide, silicon nitride, silicon oxynitride, silicon carbide,other dielectric material, or combinations thereof, and may comprise oneor multiple layers of material. The sidewall spacer 362 may be formed bydepositing a spacer material as a blanket layer over the devicestructure 300. Subsequently, a dielectric layer 364, such as atetraethyl orthosilicate (TEOS) layer, is deposited over the sidewallspacer layer 362. The dielectric layer 364 may be formed by PE-CVD,flowable chemical vapor deposition (F-CVD), or other suitable methods. Aplanarization operation is then performed on the dielectric layer 364and the sidewall spacer layer 362 such that the top surface of the topelectrode 350 is exposed after the planarization operation. Theresultant structure after the planarization operation is shown in FIG.16 . Due to the recessed top surface of the dielectric layer 310, aportion of the sidewall spacer layer 362 is below the bottom surface ofthe bottom electrode 322.

At operation 224, the method 200 (FIG. 2B) forms an inter-metaldielectric (IMD) layer 390 covering the sidewall spacer layer 362 andthe dielectric layer 364, such as shown in FIG. 17 . The IMD layer 390may comprise tetraethyl orthosilicate (TEOS) oxide, un-doped silicateglass, or doped silicon oxide such as borophosphosilicate glass (BPSG),fused silica glass (FSG), phosphosilicate glass (PSG), boron dopedsilicon glass (BSG), and/or other suitable dielectric materials. The IMDlayer 390 may be formed by PE-CVD, F-CVD, or other suitable methods. Insome embodiments, the IMD layer 396 is formed of a low-k dielectriclayer or an extreme low-k dielectric layer, to a thickness ofapproximately 2500 Å. If an extreme low-k dielectric layer is used, acuring process may be followed after depositing the extreme low-kdielectric layer to increase its porosity, lower the k value, andimprove the mechanical strengths. The operation 224 also performs one ormore CMP processes to planarize the top surface of the device structure300.

At operation 226, the method 200 (FIG. 2B) performs further steps tocomplete the fabrication of the device structure 300. For example, themethod 200 may form a via trench and an opening (not shown) in the IMDlayer 396 and deposit conductive materials therein to provideinterconnections, such as the metal line 394 and the top electrode via(TEVA) 392 that lands on the top electrode 350, such as shown in FIG. 17. The metal line 394 is part of a metallic interconnection layer, suchas a bit line (e.g., bit line BL₁ in FIG. 1C) in an MRAM cell array. Thetop electrode via 392 electrically connects an MRAM cell to the metallicinterconnection layer. In some embodiments, the top electrode via 392and the metal line 394 comprise Cu or W. The top electrode via 392 andthe metal line 394 can be formed by a damascene or dual-damasceneprocess.

FIG. 18 illustrates a cross-sectional view of the MRAM cell array inFIG. 1C along the A-A line. In FIG. 18 , a plurality of MRAM cells aredeposited sequentially along a bit line (e.g., the bit line BL₁ in FIG.1C). The top electrode via 392 and metal line 394 form a continuousconductive body extending above the MRAM cells. The metal lines 308embedded in the IMD layer 306 form word lines (e.g., the word linesWL1-WLM in FIG. 1C). The bottom electrode 322 is discontinued betweentwo adjacent MRAM cells to avoid shorting different word lines. Takedata reading operation as an example, to read data from a MRAM cell, avoltage bias is applied between a metal line 394 and a metal line 308 toselect a particular MRAM cell. Driven by the bias, a current flowsthrough a combined structure of the metal line 394, the top electrodevia 392, the top electrode 350, the MTJ 332, the bottom electrode 322,the bottom electrode via 320, and the metal line 308. One can thusobtain a series resistance of the combined structure from values of thebias and the driven current and further derive the resistance of the MTJ332. By fabricating MRAM cells with low-resistive copper-containingbottom electrode vias 320, the additional resistance other than theresistance of the MTJ 332 in the current path is reduced, whichincreases sensitivity and speed of the MRAM cells.

Although not intended to be limiting, one or more embodiments of thepresent disclosure provide many benefits to a semiconductor device andthe formation thereof. For example, embodiments of the presentdisclosure provide an MRAM cell array with low-resistivecopper-containing bottom electrode vias in achieving high sensitivityand high speed of the MRAM cell array without risking copper diffusioninto MTJs. Furthermore, formation of the MRAM cell array can be easilyintegrated into existing semiconductor fabrication processes.

In one exemplary aspect, the present disclosure is directed to a methodfor manufacturing a memory device. The method includes a method formanufacturing a memory device. The method includes forming a via trenchin a substrate; forming a via in the via trench, wherein a lower portionof the via includes a first metal and an upper portion of the viaincludes a second metal that is different from the first metal; forminga magnetic tunneling junction over the via; and forming a top electrodeover the magnetic tunneling junction. In some embodiments, the firstmetal has a lower resistivity than the second metal. In someembodiments, the first metal has a first thickness and the second metalhas a second thickness that is smaller than the first thickness. In someembodiments, a ratio of the first thickness over the second thicknessranges from about 2:1 to about 5:1. In some embodiments, the secondthickness is not less than about 120 Å. In some embodiments, the firstmetal is copper and the second metal is tungsten. In some embodiments,the method further includes prior to the forming of the via, depositinga diffusion barrier layer in the via trench. In some embodiments, themethod further includes prior to the forming of the magnetic tunnelingjunction, forming a bottom electrode over the via. In some embodiments,the method further includes recessing a top surface of the substrate,wherein the recessed top surface of the substrate remains above aninterface between the first metal and the second metal. In someembodiments, the recessed top surface is above the interface for atleast 30 Å.

In another exemplary aspect, the present disclosure is directed to amethod of forming a memory device. The method includes providing asubstrate; forming a via trench in the substrate; depositing a firstmetal in a lower portion of the via trench; depositing a second metal inan upper portion of the via trench, thereby forming a via in the viatrench, wherein the second metal has a higher resistivity than the firstmetal; forming a bottom electrode layer over the via; forming a magnetictunneling junction stack over the bottom electrode layer, wherein themagnetic tunneling junction stack includes a lower ferromagnetic layer,a tunneling barrier layer over the lower ferromagnetic layer, and anupper ferromagnetic layer over the tunneling barrier layer; and forminga top electrode layer over the magnetic tunneling junction stack. Insome embodiments, the first metal is copper and the second metal istungsten. In some embodiments, a thickness of the second metal issmaller than that of the first metal. In some embodiments, the thicknessof the second metal is at least 120 Å. In some embodiments, the methodfurther includes forming a mask layer over the top electrode layer;patterning the mask layer; and etching the top electrode layer, themagnetic tunneling junction stack, and the bottom electrode layer usingthe patterned mask layer as an etch mask. In some embodiments, theetching of the bottom electrode layer includes over etching a topportion of the substrate, such that a top surface of the substrate isbelow a bottom surface of the bottom electrode layer but above a topmostportion of the first metal in the via trench.

In yet another exemplary aspect, the present disclosure is directed to amemory device. The memory device includes a bottom electrode viaincluding a lower portion and an upper portion, wherein the lowerportion includes a first metal and the upper portion includes a secondmetal that is different than the first metal; a bottom electrodedisposed over the bottom electrode via; a magnetic tunneling junctiondisposed over the bottom electrode; and a top electrode disposed overthe magnetic tunneling junction. In some embodiments, the first metalhas a lower resistivity than the second metal. In some embodiments, thefirst metal is copper and the second metal is tungsten. In someembodiments, the memory device further includes a dielectric layersurrounding the bottom electrode via, wherein a portion of thedielectric layer is directly under and in contact with the bottomelectrode.

The foregoing outlines features of several embodiments so that those ofordinary skill in the art may better understand the aspects of thepresent disclosure. Those of ordinary skill in the art should appreciatethat they may readily use the present disclosure as a basis fordesigning or modifying other processes and structures for carrying outthe same purposes and/or achieving the same advantages of theembodiments introduced herein. Those of ordinary skill in the art shouldalso realize that such equivalent constructions do not depart from thespirit and scope of the present disclosure, and that they may makevarious changes, substitutions, and alterations herein without departingfrom the spirit and scope of the present disclosure.

What is claimed is:
 1. A semiconductor device, comprising: a substratewith a metal line embedded in the substrate; a dielectric layer disposedon the substrate; a bottom electrode via extending through thedielectric layer and landing on a top surface of the metal line, whereina lower portion of the bottom electrode via includes a first metal, andan upper portion of the bottom electrode via includes a second metalthat is different from the first metal; a bottom electrode disposed on atop surface of the bottom electrode via; a magnetic tunneling junctionstack disposed on a top surface of the bottom electrode; and a topelectrode disposed on the magnetic tunneling junction stack.
 2. Thesemiconductor device of claim 1, wherein the bottom electrode viaincludes a diffusion barrier layer covering at least sidewalls of theupper portion of the bottom electrode via.
 3. The semiconductor deviceof claim 1, wherein the first metal has a lower resistivity than thesecond metal.
 4. The semiconductor device of claim 1, wherein the firstmetal has a first thickness, and the second metal has a second thicknessthat is smaller than the first thickness.
 5. The semiconductor device ofclaim 4, wherein a ratio of the first thickness over the secondthickness ranges from about 2:1 to about 5:1.
 6. The semiconductordevice of claim 4, wherein the second thickness is not less than about120 Å.
 7. The semiconductor device of claim 1, wherein the first metalis copper, and the second metal is tungsten.
 8. The semiconductor deviceof claim 1, wherein a portion of a top surface of the dielectric layeris below the top surface of the bottom electrode via.
 9. Thesemiconductor device of claim 8, wherein the portion of the top surfaceof the dielectric layer is above an interface between the first metaland the second metal.
 10. The semiconductor device of claim 9, whereinthe portion of the top surface of the dielectric layer is above theinterface for at least 30 Å.
 11. A memory device, comprising: a bottomelectrode via including a lower portion and an upper portion, whereinthe lower portion includes a first metal, and the upper portion includesa second metal that is different than the first metal; a bottomelectrode disposed on the bottom electrode via; a magnetic tunnelingjunction stack disposed on the bottom electrode, wherein the magnetictunneling junction stack includes a lower ferromagnetic layer, atunneling barrier layer over the lower ferromagnetic layer, and an upperferromagnetic layer over the tunneling barrier layer; and a topelectrode disposed on the magnetic tunneling junction stack.
 12. Thememory device of claim 11, wherein the first metal has a lowerresistivity than the second metal.
 13. The memory device of claim 11,wherein the first metal is copper, and the second metal is tungsten. 14.The memory device of claim 11, wherein a thickness of the second metalis smaller than that of the first metal.
 15. The memory device of claim11, further comprising: a dielectric layer surrounding the bottomelectrode via, wherein a portion of the dielectric layer is directlyunder and in physical contact with a bottom surface of the bottomelectrode.
 16. The memory device of claim 11, wherein a top surface ofthe second metal has a concave profile.
 17. A semiconductor device,comprising: a dielectric layer over a substrate; a bottom electrode viathrough the dielectric layer, wherein the bottom electrode via includesa first metal layer, a second metal layer above the first metal layer,and a barrier layer in physical contact with sidewalls of the firstmetal layer and the second metal layer, the first metal layer isessentially of copper, and the second metal layer is essentially oftungsten; a bottom electrode over the bottom electrode via; a magnetictunneling junction stack over the bottom electrode; and a top electrodeover the magnetic tunneling junction stack.
 18. The semiconductor deviceof claim 17, wherein a ratio of a thickness of the first metal layerover a thickness of the second metal layer ranges from about 2:1 toabout 5:1.
 19. The semiconductor device of claim 17, wherein a topsurface of the dielectric layer has a step profile, such that a firstportion of the top surface of the dielectric layer is in physicalcontact with a bottom surface of the bottom electrode, and a secondportion of the top surface of the dielectric layer is below a topsurface of the second metal layer.
 20. The semiconductor device of claim17, further comprising: a sidewall spacer layer on sidewalls of themagnetic tunneling junction stack and the bottom electrode, wherein abottom surface of the sidewall spacer layer is below a top surface ofthe second metal layer and above an interface between the first andsecond metal layers; and a top electrode via over the top electrode.